The present invention relates to electrostatic discharge protection circuits, and in particular to an electrostatic discharge protection circuit with a cascoded trigger-switch suitable for use with over-voltage tolerant CMOS I/O buffers.
Electrostatic discharge (ESD) protection circuits, which are used to protect the I/O pads of integrated circuit (IC) chips, are well known. Such circuits typically provide a means to shunt electrostatic discharge current to ground (or another common terminal), in order to prevent damage to transistors and other sensitive components on an integrated circuit chip.
It is highly advantageous for IC chips, operating from different power supplies, to operate together within the same system. For example, it is advantageous for a CMOS chip, operating from a 3.3 volt power supply, to interface with another CMOS chip, operating from a 5 volt power supply. This requires that the I/O pads on the 3.3 volt CMOS chip tolerate xe2x80x9cover-voltagexe2x80x9d input levels as high as 5.5 volts. For the 3.3 volt CMOS chip, these over-voltage levels can be present on its input pins and/or bi-directional I/O pins (tristate(trademark) pins).
The over-voltage levels described above can cause a serious over-voltage problem for the transistors present in a conventional CMOS ESD trigger-switch circuit. This over-voltage problem causes the trigger-switch transistors to be subjected to voltages beyond their tolerances, resulting in transistor failure. Thus, in a conventional ESD trigger-switch, over-voltages can occur on p-channel transistor terminal pairs and/or n-channel transistor terminal pairs. These terminal pairs include gate-to-source, gate-to-drain, gate-to-body, drain-to-source, source-to-body and drain-to-body.
Another problem with a conventional ESD trigger-switch is false triggering, which can occur during normal power-on operation. This false triggering creates an unwanted low resistance current path between the 3.3 volt power supply (driving a 3.3 volt CMOS chip), and the 5 volt power supply (driving a 5 volt CMOS chip). This unwanted current path is a very serious problem because it degrades system noise immunity, interferes with normal I/O cell logic operation, and causes excessive power dissipation. Furthermore, this excessive power dissipation can easily induce failure in the 5 volt output drivers, the ESD protection diodes and the metal wires which are present inside the ESD protection circuit. Thus, accidental ESD trigger-switch turn-on during normal power-on IC operation is a very serious problem which must be overcome.
Thus, a need has arisen for an electrostatic discharge protection circuit with a trigger-switch that addresses the disadvantages and deficiencies of the prior art. In particular, a need has arisen for an electrostatic discharge protection circuit which (a) can be used in over-voltage applications and non-over-voltage applications; (b) keeps the power-on terminal voltages for all ESD trigger-switch transistors below their maximum values; and (c) is highly resistant to accidental turn-on during normal power-on operating conditions (due to glitches on the ESD+ power rail)
Accordingly, a novel trigger switch for an electrostatic discharge protection circuit is disclosed. In one embodiment, the trigger switch includes a first transistor with one source/drain terminal coupled to a positive electrostatic discharge node of the electrostatic discharge protection circuit. A second transistor has one source/drain terminal coupled to a negative electrostatic discharge node of the electrostatic discharge protection circuit. The second transistor has a second source/drain terminal coupled to a second source/drain terminal of the first transistor. A first resistance is coupled between the positive electrostatic discharge node and a gate terminal of the first transistor. A first capacitance is coupled between the negative electrostatic discharge node and the gate terminal of the first transistor. A second resistance is coupled between the negative electrostatic discharge node and a gate terminal of the second transistor. A second capacitance is coupled between the positive electrostatic discharge node and the gate terminal of the second transistor. The trigger switch provides a low-resistance connection between the positive and negative electrostatic discharge nodes of the electrostatic discharge protection circuit in response to an electrostatic discharge event
Advantages of the present invention include the ability to tolerate over-voltage conditions during normal power-on operation, and the ability to avoid false triggering (due to sudden transitions on the ESD power rail) during power-on operating conditions. Of course, the present invention will also protect the I/O pins of an IC during an ESD event.